The present invention relates to semiconductor memories, and more specifically relates to a memory unit capable of holding both static read/write data and independently addressable read-only data in a physical chip area no larger than that required for a comparable static read/write memory alone.
Many data-processing and similar applications require both read/write and read-only memory, commonly referred to as RAM and ROM. RAM can be implemented in two forms, static (SRAM) and dynamic (DRAM). DRAM is much more space-efficient, requiring only one FET and a capacitor per bit stored. On the other hand, although conventional SRAM requires six FETs per bit, it does not need the logic overhead and time penalty of refresh circuitry to maintain the data. SRAM is especially advantageous where small or scattered memories are used in a system or even within a single integrated-circuit chip.
Techniques are available in the prior art for combining ROM with either DRAM or SRAM in an area not significantly exceeding that required for the RAM alone. This merged memory, however, has heretofore been of the "latent image" type. That is, the read-only data exists as a controllable geometrical or electrical property of each storage cell which can be converted in place to read/write data in the same cell and then output in the same way that the read/write data are accessed. That is, the read-only data merely replace the read/write data under certain conditions, such as when power is first applied to the memory.
In any of these memories, accessing the read-only data necessitates the destruction of the read/write data in the storage cells. Such a memory may be thought of as being either read/write or read-only, but not both at the same time. For example, a 64K-bit latent-image memory has only 64K addressable locations, and has only a 16-line address bus.